000			00614nam a22001817a 4500
999			_c2824 _d2824
008			191018b2006 ||||| |||| 00| 0 eng d
020			_a9788131518489
040			_aIMU CC
082	0	0	_223 _a621.395 _bLEE
100	1		_aLee, Sunggu.
245	1	0	_aAdvanced digital logic design : _busing verilog, state machines and synthesis for FPGAs / _cSunggu Lee.
260			_aNew Delhi : _bCengage Learning, _cc 2006.
300			_axvii, 462 p. ; _c24 cm.
650		0	_aLogic design -- Data processing.
650		0	_aDigital electronics.
650		0	_aVHDL (Computer hardware description language).
942			_cBK